Synopsys Galaxy Test Reduces Test Data Volume by 40x and Application Time by 13x at STMicroelectronics
SoCBIST Solution Enables More Transition Fault Detection and Higher QoR on High-Volume Printer Chips
MOUNTAIN VIEW, Calif., Oct. 26 /PRNewswire-FirstCall/ -- Synopsys, Inc. (NASDAQ: SNPS), the world leader in semiconductor design software, announced that Synopsys' Galaxy(TM) Test flow has enabled STMicroelectronics to significantly increase its fault coverage and reduce tester time on its latest high-volume printer chipset. Using the unique DFT Compiler(TM) SoCBIST solution offered within Galaxy Test, STMicroelectronics can today reduce its test data volume by a factor of 40 and test application time by a factor of 13, detect seven percent more faults, and significantly reduce defective parts per million without increasing test costs.
"Using the SoCBIST solution in Galaxy Test, we can compress our scan test data volume by 97.25 percent to significantly reduce time on the tester while increasing the amount of defect coverage," said Loris Valenti, design manager, STMicroelectronics, Computer Peripherals Group, Printer System Division. "We estimate that, even with a test time reduction of four times over traditional scan, we can increase our transition fault coverage by seven percent. We actually were able to reach a test time reduction of 13 times and thereby reduce our defective parts per million by several hundred units over previous runs where SoCBIST was not used. In volume production, the net result is a significant improvement in the quality of shipped parts without an increase in test cost."
"High test coverage on multiple fault models is mission-critical to guarantee very high-quality test in ST's IC designs," said Roberto Mattiuzzo, design for test manager, ST-TPA R&D, Design Methodology Centre. "The Galaxy Test flow supports all the deep submicron test fault models we require and offers highly accurate defect diagnosis for fast yield-drop analysis and correction. It is now being broadly deployed in our high-volume production devices. Partnering with Synopsys has given ST the possibility to enrich the overall test solution portfolio and actively participate in the product development and qualification."
To meet quality and yield mandates with low cost, designers need a test automation solution that delivers predictable high fault coverage, provides efficient automatic test equipment (ATE) usage, and has no impact on the overall design flow. Synopsys' Galaxy Test with SoCBIST compression addresses these needs, dramatically reducing tester time and data volume compared to traditional scan.
"Synopsys' Galaxy Test is enabling market leaders to achieve highly testable designs without impacting design flows and schedules," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "By standardizing on Galaxy Test and its SoCBIST solution, ST now has a one-pass design-for-test flow that allows them to achieve fastest time-to-volume with a low test cost on their latest chipsets."
About Synopsys Galaxy Test
Galaxy Test is a comprehensive test automation solution for unified RTL-to-manufacturing test comprised of: DFT Compiler, Design Compiler(R), Physical Compiler(R), Astro(TM), DFT Compiler SoCBIST, and TetraMAX(R) ATPG. This unified solution eliminates costly iterations between design synthesis and test implementation and enables IC designers to achieve timing, area, power and DFT closure simultaneously. In addition, it provides comprehensive and easy-to-use design rule checking and validation features within SoCBIST, along with powerful BIST integration, verification, diagnostic and debug tools.
About Synopsys
Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/ .
NOTE: Synopsys, Design Compiler, Physical Compiler and TetraMAX are registered trademarks of Synopsys, Inc., Astro, and DFT Compiler and Galaxy are trademarks of Synopsys. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
CONTACT: Nancy Renzullo of Synopsys, Inc., +1-650-584-1669, or
renzullo@synopsys.com; or Sarah Seifert of Edelman Public Relations,
+1-650-429-2776, or Sarah.seifert@edelman.com, for Synopsys, Inc.
Web site: http://www.synopsys.com/
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